Publications
] Filters: Author is Xavier Martorell [Clear All Filters]
"DMA++: On the Fly Data Realignment for On-Chip Memories",
The 16th IEEE International Symposium on High-Performance Computer Architecture, Bangalore, 01/2010.
"DMA++: On the Fly Data Realignment for On-Chip Memories",
IEEE Transactions on Computers, vol. 99, no. PrePrints, Los Alamitos, CA, USA, IEEE Computer Society, 2010.
"Barcelona OpenMP Tasks Suite: A Set of Benchmarks Targeting the Exploitation of Task Parallelism in OpenMP",
38th International Conference on Parallel Processing (ICPP '09), Vienna, Austria, IEEE Computer Society, pp. 124–131, September, 2009.
"Unrolling Loops Containing Task Parallelism",
Proceedings of the 22nd International Workshop on Languages and Compilers for Parallel Computing, 09/2009.
Download: lcpc09-unroll-tasks.pdf (140.41 KB)
"Adaptive and Speculative Memory Consistency Support for Multi-core Architectures with On-Chip Local Memories",
Proceedings of the 22nd International Workshop on Languages and Compilers for Parallel Computing, 09/2009.
"A Proposal to Extend the OpenMP Tasking Model for Heterogeneous Architectures",
IWOMP'09, vol. 5568, Dresden, Germany, Springer, pp. 154-167, 06/2009.
"Automatic Prefetch and Modulo Scheduling Transformations for the Cell BE Architecture",
IEEE Transactions on Parallel and Distributed Systems, vol. 99, no. 1, Los Alamitos, CA, USA, IEEE Computer Society, 2009.
"OpenMP tasks in IBM XL compilers",
CASCON '08: Proceedings of the 2008 conference of the center for advanced studies on collaborative research, New York, NY, USA, ACM, pp. 207–221, 2008.
"Hybrid access-specific software cache techniques for the cell BE architecture",
PACT '08: Proceedings of the 17th international conference on Parallel architectures and compilation techniques, New York, NY, USA, ACM, pp. 292–302, 2008.
"Transactional Memory and OpenMP",
IWOMP '07: Proceedings of the 3rd international workshop on OpenMP, Berlin, Heidelberg, Springer-Verlag, pp. 37–53, 2008.
"Automatic Pre-Fetch and Modulo Scheduling Transformations for the Cell BE Architecture",
Languages and Compilers for Parallel Computing: 21th International Workshop, LCPC 2008, Edmonton, Canada, July 31-August 2, 2008, Revised Selected Papers: Springer, pp. 31, 2008.
"Support for OpenMP tasks in Nanos v4",
Proceedings of the 2007 conference of the Centre for Advanced Studies on Collaborative Research: IBM, pp. 256-259, October, 2007.
"Performance Analysis of Cell Broadband Engine for High Memory Bandwidth Applications",
Performance Analysis of Systems and Software, IEEE International Symmposium on, Los Alamitos, CA, USA, IEEE Computer Society, pp. 210-219, 2007.
"High-Performance Embedded Architecture and Compilation Roadmap",
T. HiPEAC, vol. 1, pp. 5-29, 2007.
"A Proposal for Error Handling in OpenMP",
International Journal of Parallel Programming, vol. 35, no. 4, pp. 393-416, 2007.
